Electronic systems often include ADC's as a basic building block in order to convert analog input signals to its digital bit representation for use with digital signal processors, memory, digital filters, and CPU's. With today's high density integration process technologies, such as nanometer CMOS, it is possible and easier to process and manipulate digital signals than analog, particularly when the power supply voltage range is low because digital bits can better overcome signal to noise issues. However, the solution has also presented a new problem. Because of the migration towards high density, smaller minimum feature size transistor technologies, ADC's designed in the traditional ways are harder to implement, particularly to achieve medium-to-high resolution.
In the medium-to-high resolution area, say, producing 10 to 16 effective number of bits, popular ADC architectures include the pipeline, sigma-delta, successive approximation (SAR), interpolation, subranging, two-stage and hybrids of these versions. However, they involve much analog circuitry or in the case of the sigma-delta, there is also a massive digital filter circuit, taking up much die area. The analog portion of the circuitry typically requires good matching among its transistors and passives components for the other architectures; therefore the circuit elements need to be large and thus take up much die area. Die area is a premium particularly on the SOC and custom ASIC chips for cost, profit and manufacture yield reasons. For example, an integrated chip for mobile telecommunications, may contain several ADC's along with many other circuit blocks. Each of the ADC's is relatively high resolution and large; so altogether, they will take up much die area.
Moreover, the design of the analog circuit sub-blocks is becoming very difficult on the small geometry size processes, say, 65 nm MOS process. The ADC architectures listed above typically are of the switched capacitor type and require amplifiers and many analog switch circuits to transfer the analog signal, charge and correction terms within the ADC. However, analog switches are very difficult to turn-off completely in the small-geometry technologies due to leakage current which adds undesirable stray charge to the capacitors in the circuit sub-block. Also the amplitude of the analog signal needs to be as large as possible for best signal-to-noise (SNR) results which is then likely to be distorted by the ordinary MOSFET switches because of the makeup of a transistor and its parasitic capacitances and resistances which are voltage amplitude dependent so that distortion is increased and SNDR (signal to noise and distortion) is worsened. Because there are so many analog switches needed in the traditional ADC architectures, it is not practical to design each switch specially (e.g. bootstrap the switch) to overcome their limitations. The other sub-blocks, such as high gain amplifiers in the ADC's, are also harder to design in the new processes. The transconductance of the transistors in the nanometer technologies is generally lower than in older processes; so the gain of a typical amplifier input transistor is lower and feedback distortion is correspondingly higher. The breakdown voltage of the transistors is lower as well so that the overall power supply used to operate the ADC is much lower than before and there is much less voltage headroom to stack up (cascode) the transistors to increase the gain of the amplifiers. So the existing ADC's which rely on these sub-blocks to perform really well, are now very difficult to design to meet performance specifications needed by the overall system applications. Further general background information relating to ADC's and sampling is given, for example, in Johns & Martin, “Analog Integrated Circuit Design”, Chapters 9, 11, 13 and 14 (1997 John Wiley & Sons).
For low resolution ADC's, requiring less than 10 bits, flash or fold-interpolate architectures are often used. There is no feedback and the element matching requirement on the comparator stage is stringent; often preamplifiers are needed to magnify the signal to overcome the offsets due to mismatches. So the ADC becomes relatively large and consumes much power. The resistive or reference ladder with which the input signal amplitude is compared to, also consumes much power if it is designed to be a stiff, constant reference.
Another class of ADC's has been described in U.S. Pat. No. 6,087,968 and in a corresponding published article by Engel Roza, “Analog to Digital Conversion via Duty-Cycle Modulation”, IEEE CAS II, Vol. 44, No. 11, November 1997. Using a figure from the patent U.S. Pat. No. 6,087,968 (now shown as FIG. 1 in this application), the analog input signal Vin is converted by element 1 into a duty cycle modulated square wave Vs that is then sampled in element 7 which is either a single-phase sampler (e.g. sample-hold circuit, sampling at specific intervals) or a poly-phase sampler. Element 8 is a digital decimating filter converting the samplings of the modulated square wave Vs into digital output bits. A drawback of this methodology is that element 1 is an asynchronous sigma-delta modulator and it also has inherent harmonic distortion. So, there is no clocking (i.e. asynchronous) in element 1 which would align the output signal Vs to other circuits in the rest of the system naturally and an additional alignment circuit is needed. And there needs to be the additional sampling circuit (e.g. sample-hold) 7 following the modulation scheme. Further, though not shown in the figure, a low-pass anti-aliasing filter or hysteresis circuit is often needed prior to the sampler 7 for noise or stability reasons. Yet further, the post-processing digital section, a decimation filter, to turn the modulated pulses into binary data and to do some out-of-band noise removal, is typically large. Therefore, an ADC based on this scheme is still quite large and consumes a fair amount of power.
In view of the above issues, there arises a need to address the drawbacks of the prior art, as is achieved by the preferred embodiments described below.